1. Field of the Invention.
The present invention relates generally to delay line circuits and more particularly to a differential signal delay line circuit operable at high frequencies.
2. Description of the Prior Art.
Encoded digital signals frequently carry information in the timing, and more particularly, the relative timing between voltage level transitions. Digital signal delay lines must exhibit high fidelity to the timing of signal level transitions and to the timing inter-relationships between transitions to preserve the data being transmitted. High fidelity becomes more critical as signal transmission frequency increases.
Digital signals are commonly transmitted as single ended signals, i.e. only one transmission path is provided. Prior art single-ended delay cells used in delay lines have relatively poor immunity to noise and tend not to exhibit precise repeatability in transition delay timing. In prior art devices, delay is provided by using a differential switch to compare ramp down voltage on a discharging capacitor with a reference voltage. The time taken to discharge the voltage level across the capacitor to the reference signal voltage level provides the delay of the cell. Fast transistor switches control charging of the delay capacitor. Switching of the transistor comes with attendant current spikes. Where a plurality of such delay cells are connected serially, and when current spikes are coupled back to the source of the reference voltage, instability and unpredictability in timing of switching of the subsequent delay cell results. Such delays may be cumulative through the delay cell chain, which results in a possible loss of intelligibility of the signal.